The present disclosure relates to a semiconductor structure, and particularly to semiconductor devices including embedded dynamic random access memory (eDRAM) cells and logic devices, and a method of manufacturing the same.
Deep trench capacitors are used in a variety of semiconductor chips for high areal capacitance and low device leakage. Typically, a deep trench capacitor provides a capacitance in the range from 4 fF (femto-Farad) to 120 fF. A deep trench capacitor may be employed as a charge storage unit in a dynamic random access memory (DRAM), which may be provided as a stand-alone semiconductor chip, or may be embedded in a system-on-chip (SoC) semiconductor chip. A deep trench capacitor may also be employed in a variety of circuit applications such as a charge pump or a capacitive analog component in a radio-frequency (RF) circuit.
Trench profiles and the depths of deep trenches formed in a semiconductor substrate depend on the areal density of deep trenches, i.e., on the fraction of the area of the deep trenches with respect to the total area of a substrate in which deep trenches are to be formed. Further, local density of deep trenches can affect the profiles and the depths of the deep trenches. In a semiconductor chip including embedded DRAM cells and logic devices, therefore, structural features and performance of deep trench capacitors can depend on the area of logic devices within the vicinity of the deep trench capacitors. Therefore, a scheme is desired for alleviating the dependence of the structural features and performance of deep trench capacitors on the local device environment.